1. Field of the Invention
The present invention relates generally to a direct access storage device (DASD) of the type utilizing partial-response signaling and maximum-likelihood (PRML) detection together with digital filtering, and more particularly to apparatus and method for providing equalization adjustment for a digital filter in a PRML magnetic recording channel.
2. Description of the Prior Art
Computers often include auxiliary memory storage units having media on which data can be written and from which data can be read for later use. Disk drive units incorporating stacked, commonly rotated rigid magnetic disks are used for storage of data in magnetic form on the disk surfaces. Data is recorded in concentric, radially spaced data information tracks arrayed on the surfaces of the disks. Transducer heads driven in a path toward and away from the drive axis write data to the disks and read data from the disks. A PRML channel can be used to achieve high data density in writing and reading digital data on the disks.
To obtain full advantage of the PRML channel, the received signal or the read signal must be passed through a specially designed equalizing filter which produces at its output a signal spectrum corresponding to the wave shape for which the maximum-likelihood detector is designed. When using digital filtering in a PRML system, the filter is located between an analog-to-digital converter (ADC) and other signal processing hardware which controls the system and performs the detection.
Various equalizer adjustments have been implemented during data recovery in PRML to improve hard error rate. Typically, disadvantages of the known equalizer arrangements include first, the adaptive equalizer can exhibit systematic error in converging to a proper value for the adaptive constant, depending on offtrack conditions, external noise, and magnetic instabilities. Second, significant analog path frequency response changes which may occur in the magnetics or in the filter path may cause convergence problems due to compromise initial conditions in the adaptive loop.
U.S. patent application Ser. No. 07/851,817 filed Mar. 16, 1992 by Jonathan Darrel Coker, Richard Leo Galbraith and Pablo Alejandro Ziperovich and assigned to the present assignee, discloses a distributed arithmetic (DA) digital filter having many taps, such as a ten 10-tap filter implemented in RAM. The disclosed DA digital filter is configured with an automatic equalization architecture that does not require an adaptive loop. As a result the partial-response digital filter (PRDF) gained significant advantage in power and speed as compared to an adaptive filter that would be directly in a critical speed path of the module, and also simplicity of design. The disclosed PRDF provides 64 equalizations that can be used for example to accommodate 15 heads and 10 radial bands or 150 locations which may be marginally acceptable.
With disk files having a large number of disks, for example 12 disks, more effective equalizations are required. It is desirable to extend the power of the automatic equalization architecture significantly. Further it is desirable to provide an automatic equalization architecture that will allow simpler and faster data recovery procedure (DRP) steps without increasing the palette RAM size.